On the Ultimate Limits of IC Inductors—An RF MEMS Perspective

Inductors are playing an ever-increasing role in RFICs, motivating extensive work on the development of structures to achieve optimized performance. In this paper we review the different approaches being explored to achieve high inductor Q and self-resonance frequency, in the context of conventional CMOS and BiCMOS processes, and examine how the application of RF MEMS techniques may effect superior monolithic inductor performance, and at what expense. Introduction Inductors are playing an ever-increasing role in RFICs [14]. In addition to being frequently employed in passive tuning circuits, or as high-impedance chokes, many novel techniques to achieve low-voltage operation in advanced silicon IC processes rely on the negligible DC voltage drop across inductors when utilized as loads or as emitter/source degenerators [3-4]. When fabricated in a planar process, the trace capacitance to ground tends to lower the inductor selfresonance frequency, and the substrate conductivity tends to lower its quality factor (Q) [5]. While optimization of the spiral geometry and line width [2], [5-6] is essential to tailor the frequency of maximum Q, this exercise only addresses minimization of the trace ohmic losses and substrate capacitance. Thus, a number of attempts to use conventional processing techniques to diminish the substrate losses created by eddy currents induced by the magnetic field of the spiral have been pursued. For instance, while [5] introduced blocking p-n-p junctions in the path of the eddy current flowing in an underlying p layer, [7] introduced a patterned metal ground shield to also block the eddy current. These, and similar approaches, however, only achieve modest relative improvements and, certainly, do not achieve Qs much greater than 10, or self-resonance frequencies greater than a few GHz. The fabrication flexibility afforded by microelectromechanical systems (MEMS) technology is expected to greatly enhance the performance of monolithic RF passive devices but, by how much and at what expense? In this paper, for the first time, we present an analysis of RFIC inductors build in both conventional and RF MEMS technologies, and establish a projection of their ultimate achievable performance limits. Conventional RFIC Inductors The fundamental monolithic inductor is usually implemented as a spiral trace disposed on the passivation layer over a silicon substrate, Fig. 1. The connection to the innermost turn is effected either through an underpass, or via an airbridge. An examination of the fundamental structure reveals the following sources of performance degradation [9]: (1) Eddy current-induced losses, due to magnetic field penetration into both the substrate and adjacent traces; (2) Trace resistance, due to its finite conductivity and width; (3) Substrate capacitance and ohmic losses, due to their shunting of the input signal to ground and, thus, causing less than the input signal to reach the output. These loss elements are embodied by the circuit model of Fig. 2 [10]. Figure 1. Planar inductor [8].